1. Field of the Invention
The present invention relates to an image processing apparatus having a variable magnification/reduction function, and more particularly to a digital image processing apparatus such as a digital copying machine which can electrically magnify or reduce image data.
2. Description of the Prior Art
FIG. 1 shows a prior art image processing apparatus of the above type.
In FIG. 1, an image data is outputted from image reader 1 in synchronism with a frequency f.omega. and the image data is magnified or reduced by a factor of 0 to 2. A clock generator 2 generates a clock signal having the frequency f.omega. and a clock signal having a frequency 2f.omega. which is used to magnify the image data by a factor of up to two.
The clock signal having the frequency 2f.omega. is supplied to a clock changing circuit (variable clock circuit) 3 where the frequency of the clock signal is multipled by a factor of M (M=0 to 1) in response to a magnification factor control signal A to produce a write clock signal which is used to write the image data into a memory 4.
The written image data is read from the memory 4 in synchronism with a clock signal having a frequency F.sub.R which is generated by the clock generator 5. In the circuit shown in FIG. 1, the image data is written into the memory 4 by the write clock having a frequency higher than f.omega., that is, the frequency M2f.omega. (0.5.ltoreq.M.ltoreq.1) to magnify the image so that the image data is interpolated.
On the other hand, to reduce the image, the image data is written into the memory 4 by the write clock having the frequency M2f.omega. (0.ltoreq.M&lt;0.5) which is lower than the frequency f.omega. so that the image data is interlaced. When the frequency of the write clock is equal to f.omega., the image data of the equal scale is produced.
In the image processing apparatus which uses the magnification/reduction system shown in FIG. 1, the clock signal having the frequency 2f.omega. is necessary to magnify the image by the factor of two. Accordingly, the variable clock circuit 3 (for example, Texas Instrument rate multiplier 7497) and the memory 4 (for example, Intel 2147 high speed static RAM) must be able to operate in a high frequency region and a problem may arise in a stable operation of the circuit.
When f.omega. is 10 MHz and a magnification factor of ten is required, the variable clock circuit 3 and the memory 4 must be operated by the write clock signal having a frequency of as high as 10f.omega.=100 MHz. This is difficult to attain.
Further, since the data is interpolated in the magnification mode, the memory needs a capacity equal to the image data multiplied by the magnification factor (&gt;1) in order to magnify the image data. Accordingly, if the number of one line of image data is 4096 bits, the memory 4 needs the capacity equal to 4096.times.2=8192 its per line in order to magnify the image data by the factor of two in a main scan direction. When the Intel RAM 2147 is used, two such RAM's are required. This increases the cost.